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Reduction of latency and resource usage in bit-level pipelined data ptahs for FPGAs

Reduction of latency and resource usage in bit-level pipelined data ptahs for FPGAs
Reduction of latency and resource usage in bit-level pipelined data ptahs for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimised towards specifice applications are used. This paper describes a novel methodology for the design of generic bit-level pipelined data paths that have the low resource usage and latency of specifically tailored architectures but still allow the fexiable trade-off between speed and resource requirements inherent in generic circuits. This is achieved through the elimination of all skew and alignment flip-flops from the data path whilst still maintaining the original pipelining scheme, hence allowing more compact structures with decreased circuit delays. The resulting low latency is beneficial in the realisation of all recursive signal processing applications and the reduced resource usage enables particularly the efficient FPGA realisation of high performance signal processing functions. The design process is illustrated through the high level-based FPGA realisation of a 9th-order wave digital filter, demonstrating that high performance and efficient resource usage are possible. For example, the implementation of a digital filter with 10-bit signal word length and 6-bit coefficients using a Xilinx XC4013XL-1 device supports sample rates of 2.5MHz
1581130880
ACM/SIGDA
Kollig, P.
d7f7aada-a447-407b-857a-1fa6250083a4
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Kollig, P.
d7f7aada-a447-407b-857a-1fa6250083a4
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Kollig, P. and Al-Hashimi, B.M. (1999) Reduction of latency and resource usage in bit-level pipelined data ptahs for FPGAs

Record type: Other

Abstract

Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimised towards specifice applications are used. This paper describes a novel methodology for the design of generic bit-level pipelined data paths that have the low resource usage and latency of specifically tailored architectures but still allow the fexiable trade-off between speed and resource requirements inherent in generic circuits. This is achieved through the elimination of all skew and alignment flip-flops from the data path whilst still maintaining the original pipelining scheme, hence allowing more compact structures with decreased circuit delays. The resulting low latency is beneficial in the realisation of all recursive signal processing applications and the reduced resource usage enables particularly the efficient FPGA realisation of high performance signal processing functions. The design process is illustrated through the high level-based FPGA realisation of a 9th-order wave digital filter, demonstrating that high performance and efficient resource usage are possible. For example, the implementation of a digital filter with 10-bit signal word length and 6-bit coefficients using a Xilinx XC4013XL-1 device supports sample rates of 2.5MHz

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More information

Published date: February 1999
Additional Information: Organisation: ACM/SIGDA Address: USA
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 251400
URI: http://eprints.soton.ac.uk/id/eprint/251400
ISBN: 1581130880
PURE UUID: 6917c244-1e3e-4b58-bfbf-6aef344c90bf

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Date deposited: 03 Apr 2000
Last modified: 18 Jul 2017 10:09

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Contributors

Author: P. Kollig
Author: B.M. Al-Hashimi

University divisions

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