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Efficient BIST hardware insertion with low test application time for synthesized data paths

Efficient BIST hardware insertion with low test application time for synthesized data paths
Efficient BIST hardware insertion with low test application time for synthesized data paths
New and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST enviroment. Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility calsses and n-input k-bit comparators are used to check the results. The test application time is computed using an incremental test scheduling approach. An existing test scheduling algorithm is modified to obtain an efficient trade-off between the algorithm complexity and testable design space exploration. A cost function based on both test application time and area overhead is defined and a tabu search-based heuristic capable of exploring the solution space in a very rapid time is presented. To reduce the computational time testable design space exploration is carried out in 2 phases: test application time reduction phase and BIST area reduction phase. Experimental results are included confirming the efficiency of the proposed methodology.
0769500781
289-295
Nicolici, N.
9be70b5e-becc-4ec4-a564-14758ef4f03c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, N.
9be70b5e-becc-4ec4-a564-14758ef4f03c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Nicolici, N. and Al-Hashimi, B.M. (1999) Efficient BIST hardware insertion with low test application time for synthesized data paths At IEEE/ACM Design, Automation and Test in Europe. , pp. 289-295.

Record type: Conference or Workshop Item (Other)

Abstract

New and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST enviroment. Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility calsses and n-input k-bit comparators are used to check the results. The test application time is computed using an incremental test scheduling approach. An existing test scheduling algorithm is modified to obtain an efficient trade-off between the algorithm complexity and testable design space exploration. A cost function based on both test application time and area overhead is defined and a tabu search-based heuristic capable of exploring the solution space in a very rapid time is presented. To reduce the computational time testable design space exploration is carried out in 2 phases: test application time reduction phase and BIST area reduction phase. Experimental results are included confirming the efficiency of the proposed methodology.

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More information

Published date: March 1999
Additional Information: Organisation: ACM SIGDA, IEEE Computer Socitey Address: USA
Venue - Dates: IEEE/ACM Design, Automation and Test in Europe, 1999-03-01
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 251403
URI: http://eprints.soton.ac.uk/id/eprint/251403
ISBN: 0769500781
PURE UUID: f4d3b7f8-5ba5-4938-90fe-fbd19c5751ef

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Date deposited: 13 Apr 2000
Last modified: 18 Jul 2017 10:09

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Contributors

Author: N. Nicolici
Author: B.M. Al-Hashimi

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