Kollig, P. and Al-Hashimi, B.M.
FPGA Implementation of high performance FIR Filters
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This paper describes the design and implementation of high performance, high speed linear phase FIR filters using FPGA technology. To demonstrate the design process, the implementation of a 64 tap filter with 60dB attenuation at 0.28fs, 12dB attenuation at 0.25fs and a passband ripple of <0.02dB up to 0.22fs is included. The filter with 10bit signal and 8bit coefficients has been realised on a Xilinx XC4006E device and operates at a sampling frequency of 1.4MHz.
Conference or Workshop Item
||Electronic & Software Systems
||03 Nov 1999
||17 Apr 2017 23:42
|Further Information:||Google Scholar|
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