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FPGA Implementation of high performance FIR Filters

Record type: Conference or Workshop Item (Other)

This paper describes the design and implementation of high performance, high speed linear phase FIR filters using FPGA technology. To demonstrate the design process, the implementation of a 64 tap filter with 60dB attenuation at 0.28fs, 12dB attenuation at 0.25fs and a passband ripple of <0.02dB up to 0.22fs is included. The filter with 10bit signal and 8bit coefficients has been realised on a Xilinx XC4006E device and operates at a sampling frequency of 1.4MHz.

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Citation

Kollig, P. and Al-Hashimi, B.M. (1997) FPGA Implementation of high performance FIR Filters , pp. 2240-43.

More information

Published date: June 1997
Additional Information: Address: IEEE
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 251503
URI: http://eprints.soton.ac.uk/id/eprint/251503
PURE UUID: fe8939a2-b385-440c-a3c0-2a37f6ef11d0

Catalogue record

Date deposited: 03 Nov 1999
Last modified: 18 Jul 2017 10:09

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Contributors

Author: P. Kollig
Author: B.M. Al-Hashimi

University divisions


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