High performance distributed arithmetic FPGA decimators for video frequency applications

Living, J., AL-Hashimi, B.M. and Moniri, M. (1998) High performance distributed arithmetic FPGA decimators for video frequency applications. pp. 294-297 .

Record type: Conference or Workshop Item (Other)

Abstract

This paper describes a method for implementing high performance integer decimators for video-frequency applications using FPGAs. The decimators are derived from polyphase decomposition of an FIR filter prototype and implemented using a modified distributed arithmetic look-up table architecture previously only suitable for low-order specifications. A new pseudo floating point method of coefficient representation is described, allowing high-order filters to be achieved with the limited resources of FPGAs. Furthermore, a RAM based delay operator is used to provide an efficient decimator sample delay section in place of the flip-flop realisation normally employed. To demonstrate the design methodology, the implementation of a 2:1 decimator for 27MHz oversampled video signals using a Xilinx XC4013E FPGA is included.

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