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High performance distributed arithmetic FPGA decimators for video frequency applications

Living, J., AL-Hashimi, B.M. and Moniri, M. (1998) High performance distributed arithmetic FPGA decimators for video frequency applications , pp. 294-297.

Record type: Conference or Workshop Item (Other)

Abstract

This paper describes a method for implementing high performance integer decimators for video-frequency applications using FPGAs. The decimators are derived from polyphase decomposition of an FIR filter prototype and implemented using a modified distributed arithemtic look-up table architecture previously only suitable for low-order specifications. A new pseudo floating point method of coefficient representation is described, allowing high-order filters to be achieved with the limited resources of FPGAs. Furthemore, a RAM based delay operator is used to provide an efficient decimator sample dealy section in place of the flip-flop realisation normally employed. To demonstrate the design methodology, the implementation of a 2:1 decimator for 27MHz oversampled video signals using a Xilinx XC4013E FPGA is included.

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More information

Published date: September 1998
Additional Information: Address: USA
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 251545
URI: http://eprints.soton.ac.uk/id/eprint/251545
PURE UUID: b90a0e36-c658-40a9-bfef-3a3a118fe429

Catalogue record

Date deposited: 03 Nov 1999
Last modified: 18 Jul 2017 10:09

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Contributors

Author: J. Living
Author: B.M. AL-Hashimi
Author: M. Moniri

University divisions

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