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FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz

FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz
FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz
Living, J
9be8483d-f7b0-4bfd-8bcc-8c9b16829e91
Al-Hashimi, B.M.
e8058bef-ffc0-4c7c-9233-4cef40d689b4
Living, J
9be8483d-f7b0-4bfd-8bcc-8c9b16829e91
Al-Hashimi, B.M.
e8058bef-ffc0-4c7c-9233-4cef40d689b4

Living, J and Al-Hashimi, B.M. (1998) FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz.

Record type: Conference or Workshop Item (Other)

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More information

Published date: October 1998
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 251546
URI: http://eprints.soton.ac.uk/id/eprint/251546
PURE UUID: 14d42a4d-e385-4c18-965d-e840def5cd3b

Catalogue record

Date deposited: 03 Nov 1999
Last modified: 29 Jan 2020 15:07

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Contributors

Author: J Living
Author: B.M. Al-Hashimi

University divisions

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