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CMOS Design of Group Delay Equaliser

Al-Hashimi, B.M., Dudek, F. and Sun, Y. (2000) CMOS Design of Group Delay Equaliser , pp. 163-169.

Record type: Conference or Workshop Item (Other)


Two new current-mode allpass sections based on dual-output OTAs and triple-output OTAs and grounded capacitors are described. Techniques to minimise the equaliser active device count and efficiently simulate grounded resistors are proposed. A 5th-order group delay equaliser based on the presented allpass sections is designed and simulated using multiple-output CMOS OTAs. Numercial optimisation is used to determine the equaliser order and parameters. SPICE simulation results are given demonstrating that the equaliser can effectively compensate the dealy characteristic of 4th-order 4MHz lowpass Chebyshev filter to <8ns ripple over 90% of the filter passband.

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Published date: August 2000
Additional Information: Address: USA
Organisations: Electronic & Software Systems


Local EPrints ID: 251551
PURE UUID: b0b6b259-70b2-4c78-82fb-6c1e7ab1c071

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Date deposited: 21 Jun 2000
Last modified: 18 Jul 2017 10:09

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Author: B.M. Al-Hashimi
Author: F. Dudek
Author: Y. Sun

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