Analogue fault modelling and simulation for supply current monitoring
Analogue fault modelling and simulation for supply current monitoring
Fault simulation of analogue circuits is a very CPU intensive task. This paper describes a technique to increase the speed of fault simulation. The effects of bridging faults within operational amplifiers have been classified according to the externally observable behaviour reducing the number of fault simulations by two thirds. Parameterisable macromodels have been written in which both fault-free specifications and faulty effects can be modelled. The supply current is also modelled. These macromodels have been verified by embedding within a larger circuit, and have been shown to accurately model fault-free and faulty behaviour, and to propagate faulty effects correctly. The macromodels simulate about 7.5 times faster than the full transistor model.
547-552
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Chalk, C.
103fc026-0f98-4aa4-a4df-893ae204dac7
Wilkins, B.R.
b7b6acfe-93b9-4d4a-a5ac-b52438ab26ca
14 March 1996
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Chalk, C.
103fc026-0f98-4aa4-a4df-893ae204dac7
Wilkins, B.R.
b7b6acfe-93b9-4d4a-a5ac-b52438ab26ca
Zwolinski, M., Chalk, C. and Wilkins, B.R.
(1996)
Analogue fault modelling and simulation for supply current monitoring.
In EDTC '96: Proceedings of the 1996 European conference on Design and Test.
IEEE.
.
Record type:
Conference or Workshop Item
(Paper)
Abstract
Fault simulation of analogue circuits is a very CPU intensive task. This paper describes a technique to increase the speed of fault simulation. The effects of bridging faults within operational amplifiers have been classified according to the externally observable behaviour reducing the number of fault simulations by two thirds. Parameterisable macromodels have been written in which both fault-free specifications and faulty effects can be modelled. The supply current is also modelled. These macromodels have been verified by embedding within a larger circuit, and have been shown to accurately model fault-free and faulty behaviour, and to propagate faulty effects correctly. The macromodels simulate about 7.5 times faster than the full transistor model.
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Published date: 14 March 1996
Venue - Dates:
European Design and Test Conference, , Paris, France, 1996-03-11 - 1996-03-14
Organisations:
EEE
Identifiers
Local EPrints ID: 251842
URI: http://eprints.soton.ac.uk/id/eprint/251842
PURE UUID: 285d5cc6-51f4-4f71-b469-c097767c75c7
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Date deposited: 12 Nov 1999
Last modified: 20 Feb 2024 02:32
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Contributors
Author:
M. Zwolinski
Author:
C. Chalk
Author:
B.R. Wilkins
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