Spinks, S.J., Chalk, C.D., Zwolinski, M. and Bell, I.M. (1997) Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations.
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Published date: 1997
Additional Information:
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Organisation: IEEE
Organisations:
EEE
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Local EPrints ID: 251846
URI: http://eprints.soton.ac.uk/id/eprint/251846
PURE UUID: c0d6e712-a1a9-4041-bb02-27ea3cbfc502
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Date deposited: 12 Nov 1999
Last modified: 09 Jan 2022 02:36
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Contributors
Author:
S.J. Spinks
Author:
C.D. Chalk
Author:
M. Zwolinski
Author:
I.M. Bell
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