Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations


Spinks, S.J., Chalk, C.D., Zwolinski, M. and Bell, I.M. (1997) Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations

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Item Type: Other
Additional Information: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Organisation: IEEE
Organisations: EEE
ePrint ID: 251846
Date :
Date Event
1997Published
Date Deposited: 12 Nov 1999
Last Modified: 17 Apr 2017 23:40
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/251846

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