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A gate delay expression for the optimisation of ECL processes

A gate delay expression for the optimisation of ECL processes
A gate delay expression for the optimisation of ECL processes
Chor, E F
66328b6e-8b0f-412e-b94c-8d858baf222d
Brunnschweiler, A
2d39ef7c-b95e-476c-b435-316b6618a565
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Chor, E F
66328b6e-8b0f-412e-b94c-8d858baf222d
Brunnschweiler, A
2d39ef7c-b95e-476c-b435-316b6618a565
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Chor, E F, Brunnschweiler, A and Ashburn, P (1988) A gate delay expression for the optimisation of ECL processes.

Record type: Other

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More information

Published date: 1988
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 251863
URI: https://eprints.soton.ac.uk/id/eprint/251863
PURE UUID: 81af19e0-93f8-47a1-8205-43b75d345b8c

Catalogue record

Date deposited: 15 Nov 1999
Last modified: 04 Dec 2017 17:32

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