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Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits

Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits
Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. The technique is based on classifying scan latches into compatible, incompatiable and independent scan latches. Based on thier classification scan latches are partitioned into multiple scan chains. A new test application strategy which applies an extra test vector to primary inputs while shifting out test responses for each scan chain, minimizes power dissipation by eliminating the spurious transitions which occur in the combinational part of the circuit. Unlike previous approches which are test vector and scan latch order dependent and hence are not able to handle large circuits due to the complexity of the design space, this paper shows that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time. For example, in the case of bech mark circuit s15850 it takes <3600s in computational time and < 1% in test area and test data overhead to achieve 80% savings in power dissipation.
715-722
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Nicolici, Nicola and Al-Hashimi, Bashir M. (2000) Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits At IEEE/ACM Design, Automation and Test in Europe (DATE). , pp. 715-722.

Record type: Conference or Workshop Item (Other)

Abstract

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. The technique is based on classifying scan latches into compatible, incompatiable and independent scan latches. Based on thier classification scan latches are partitioned into multiple scan chains. A new test application strategy which applies an extra test vector to primary inputs while shifting out test responses for each scan chain, minimizes power dissipation by eliminating the spurious transitions which occur in the combinational part of the circuit. Unlike previous approches which are test vector and scan latch order dependent and hence are not able to handle large circuits due to the complexity of the design space, this paper shows that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time. For example, in the case of bech mark circuit s15850 it takes <3600s in computational time and < 1% in test area and test data overhead to achieve 80% savings in power dissipation.

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More information

Published date: March 2000
Additional Information: Organisation: ACM SIGDA, IEEE Computer Socitey
Venue - Dates: IEEE/ACM Design, Automation and Test in Europe (DATE), 2000-03-01
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 251928
URI: http://eprints.soton.ac.uk/id/eprint/251928
PURE UUID: 1628eb9d-c468-44a8-96ce-f9a93460a22c

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Date deposited: 06 Apr 2000
Last modified: 18 Jul 2017 10:07

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Contributors

Author: Nicola Nicolici

University divisions

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