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FPGA based video signal decimators for sample rate reduction from 27/28.64 MHz to 13.5/14.32 MHz

Living, J. and Al-Hashimi, B.M. (1999) FPGA based video signal decimators for sample rate reduction from 27/28.64 MHz to 13.5/14.32 MHz , pp. 38-42.

Record type: Conference or Workshop Item (Other)

Abstract

This paper describes the design and implementation of FPGA based decimator for 2:1 oversampled video signals. The maximum input data rate to be accommodated is 28.64Ms.s-1 for composite (YUV) signals while the most critical frequency response is defined by the CCIR 601 specification for luminance (Y) signals. An ossociated constant group delay characteristic is readilyb achieved by FIR filtering, leading to use of a polyphase network for decimation. The all-pass filters in the polyphase are realised using a distributed arithmetic architecture converted for digit-serial operation and a modular, resource efficent connection scheme for higher-order filters is considered. The decimators have been implemented using Xilinx XC4000E series FPGAs with -3 speed grade parts achieving sample processing rates of 30Ms.s[1, clearly meeting the required performance.

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More information

Published date: September 1999
Additional Information: Organisation: IEEE, IEE
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 252023
URI: http://eprints.soton.ac.uk/id/eprint/252023
PURE UUID: ae238d25-62c9-410b-a7c6-1f70e1546977

Catalogue record

Date deposited: 03 Apr 2000
Last modified: 18 Jul 2017 10:07

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Contributors

Author: J. Living
Author: B.M. Al-Hashimi

University divisions

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