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Power Minimisation Techniques for Testing Low Power VLSI Circuits

Nicolici, Nicola and Al-Hashimi, Bashir M (2000) Power Minimisation Techniques for Testing Low Power VLSI Circuits At IEE Postgraduate Research and Electronics and Photonics (PREP). , pp. 7-12.

Record type: Conference or Workshop Item (Other)


Power dissipation has becomea significant concern in deep submicron VLSI and a substantial amount of research has been conducted in order to develop power minimisation techniques. While many techniques have investigated power minimisation during the functional mode of operation, an emerging research area is power minimisation during testing. Power minimisation during test application is important since it increases yield and reliability. This paper presents a review of power minimisation techniques for testing low power VLSI circuits recently proposed by the authors.

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Published date: April 2000
Additional Information: Organisation: EPSRC
Venue - Dates: IEE Postgraduate Research and Electronics and Photonics (PREP), 2000-04-01
Organisations: Electronic & Software Systems


Local EPrints ID: 252644
PURE UUID: 2c8d221b-b8ea-4493-9a64-4e1008037c30

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Date deposited: 12 Apr 2000
Last modified: 18 Jul 2017 10:03

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Author: Nicola Nicolici

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