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Si0.64 Ge0.36/Si Heterojunction MOSFETs: design, fabrication and evaluation

Si0.64 Ge0.36/Si Heterojunction MOSFETs: design, fabrication and evaluation
Si0.64 Ge0.36/Si Heterojunction MOSFETs: design, fabrication and evaluation
Incorporation of pseudomorphic SiGe layers into Si CMOS has prospects of improving the hole channel mobility to match that of the bulk silicon electron channel. Current 0.25 µm MOS technologies require sheet densities around 1013 cm-2. This requires a Si capping layer thickness of ~ 2nm between the Si0.64 Ge0.36 channel and the gate oxide.
Braithwaite, G.
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Grasby, T.J.
d39df2d0-9fa3-40ac-afa6-8c0ea15c1e15
Palmer, M.J.
dfaee826-0401-4b8e-bfde-c5653127d8e1
Prest, M.J.
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Parry, C.P.
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Whall, T.E.
875dbadb-3f0d-4706-8496-19c5ab15e162
Parker, E.H.C.
e64c94b4-1029-4f6d-9ff2-6d305907f79c
Waite, A.M.
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Evans, A.G.R.
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Roy, S.
e666eef6-02d8-4e39-bd06-2402d3cf77ec
Asenov, A.
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Braithwaite, G.
e398b9b0-9923-47a4-803e-f64d204f4e69
Grasby, T.J.
d39df2d0-9fa3-40ac-afa6-8c0ea15c1e15
Palmer, M.J.
dfaee826-0401-4b8e-bfde-c5653127d8e1
Prest, M.J.
11bb457a-1e4d-4574-9948-b0c6ce64feeb
Parry, C.P.
49dcf100-e355-4c01-a9e7-f7bde2ec4aad
Whall, T.E.
875dbadb-3f0d-4706-8496-19c5ab15e162
Parker, E.H.C.
e64c94b4-1029-4f6d-9ff2-6d305907f79c
Waite, A.M.
d021f13b-f8dd-4398-89d1-bb9cf308072c
Evans, A.G.R.
c4a3f208-8fd9-491d-870f-ce7eef943311
Roy, S.
e666eef6-02d8-4e39-bd06-2402d3cf77ec
Asenov, A.
0c4a44b6-b45c-445c-841c-7294dfd67205

Braithwaite, G., Grasby, T.J., Palmer, M.J., Prest, M.J., Parry, C.P., Whall, T.E., Parker, E.H.C., Waite, A.M., Evans, A.G.R., Roy, S. and Asenov, A. (1999) Si0.64 Ge0.36/Si Heterojunction MOSFETs: design, fabrication and evaluation. International Joint Conference on Silicon Epitaxy and Heterostructures (IJC-Si) (Si-MBE8) (Si-HS3), Research Institute of Electrical Communication, Japan.

Record type: Conference or Workshop Item (Paper)

Abstract

Incorporation of pseudomorphic SiGe layers into Si CMOS has prospects of improving the hole channel mobility to match that of the bulk silicon electron channel. Current 0.25 µm MOS technologies require sheet densities around 1013 cm-2. This requires a Si capping layer thickness of ~ 2nm between the Si0.64 Ge0.36 channel and the gate oxide.

Full text not available from this repository.

More information

Published date: September 1999
Additional Information: International Joint Conference on Silicon Epitaxy and Heterostructures (IJC-Si) (Si-MBE8) (Si-HS3). Organisation: Research Institute of Electrical Communication, Tohoku University
Venue - Dates: International Joint Conference on Silicon Epitaxy and Heterostructures (IJC-Si) (Si-MBE8) (Si-HS3), Research Institute of Electrical Communication, Japan, 1999-08-31
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 252697
URI: http://eprints.soton.ac.uk/id/eprint/252697
PURE UUID: 683bdd32-4db6-47d5-a1f8-5653a5357415

Catalogue record

Date deposited: 09 May 2000
Last modified: 05 Aug 2020 16:33

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