The University of Southampton
University of Southampton Institutional Repository

Si0.64 GE0.36/Si Heterojunction MOSFETs: Design, Fabrication and Evaluation

Si0.64 GE0.36/Si Heterojunction MOSFETs: Design, Fabrication and Evaluation
Si0.64 GE0.36/Si Heterojunction MOSFETs: Design, Fabrication and Evaluation
Incorporation of pseydomorphic SiGe layers into Si CMOS has prospects of improving the hole channel mobility to match that of the bulk silicon electron channel. Current 0.25 um MOS technologies require sheet densities around 1013 cm-2. This requires a Si capping layer thickness of ~ 2nm between the Si0.64 GE0.36 channel and the gate oxide.
Braithwaite, G
e398b9b0-9923-47a4-803e-f64d204f4e69
Grasby, T J
d39df2d0-9fa3-40ac-afa6-8c0ea15c1e15
Palmer, M J
dfaee826-0401-4b8e-bfde-c5653127d8e1
Prest, M J
11bb457a-1e4d-4574-9948-b0c6ce64feeb
Parry, C P
49dcf100-e355-4c01-a9e7-f7bde2ec4aad
Whall, T E
875dbadb-3f0d-4706-8496-19c5ab15e162
Parker, E H C
e64c94b4-1029-4f6d-9ff2-6d305907f79c
Waite, A M
d021f13b-f8dd-4398-89d1-bb9cf308072c
Evans, A G R
c4a3f208-8fd9-491d-870f-ce7eef943311
Roy, S
e666eef6-02d8-4e39-bd06-2402d3cf77ec
Asenov, A
0c4a44b6-b45c-445c-841c-7294dfd67205
Braithwaite, G
e398b9b0-9923-47a4-803e-f64d204f4e69
Grasby, T J
d39df2d0-9fa3-40ac-afa6-8c0ea15c1e15
Palmer, M J
dfaee826-0401-4b8e-bfde-c5653127d8e1
Prest, M J
11bb457a-1e4d-4574-9948-b0c6ce64feeb
Parry, C P
49dcf100-e355-4c01-a9e7-f7bde2ec4aad
Whall, T E
875dbadb-3f0d-4706-8496-19c5ab15e162
Parker, E H C
e64c94b4-1029-4f6d-9ff2-6d305907f79c
Waite, A M
d021f13b-f8dd-4398-89d1-bb9cf308072c
Evans, A G R
c4a3f208-8fd9-491d-870f-ce7eef943311
Roy, S
e666eef6-02d8-4e39-bd06-2402d3cf77ec
Asenov, A
0c4a44b6-b45c-445c-841c-7294dfd67205

Braithwaite, G, Grasby, T J, Palmer, M J, Prest, M J, Parry, C P, Whall, T E, Parker, E H C, Waite, A M, Evans, A G R, Roy, S and Asenov, A (1999) Si0.64 GE0.36/Si Heterojunction MOSFETs: Design, Fabrication and Evaluation

Record type: Other

Abstract

Incorporation of pseydomorphic SiGe layers into Si CMOS has prospects of improving the hole channel mobility to match that of the bulk silicon electron channel. Current 0.25 um MOS technologies require sheet densities around 1013 cm-2. This requires a Si capping layer thickness of ~ 2nm between the Si0.64 GE0.36 channel and the gate oxide.

Full text not available from this repository.

More information

Published date: September 1999
Additional Information: International Joint Conference on Silicon Epitaxy and Heterostructures (IJC-Si) (Si-MBE8) (Si-HS3). Organisation: Research Institute of Electrical Communication, Tohoku University
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 252697
URI: http://eprints.soton.ac.uk/id/eprint/252697
PURE UUID: 683bdd32-4db6-47d5-a1f8-5653a5357415

Catalogue record

Date deposited: 09 May 2000
Last modified: 04 Dec 2017 17:32

Export record

Contributors

Author: G Braithwaite
Author: T J Grasby
Author: M J Palmer
Author: M J Prest
Author: C P Parry
Author: T E Whall
Author: E H C Parker
Author: A M Waite
Author: A G R Evans
Author: S Roy
Author: A Asenov

University divisions

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×