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In-line Test of Synthesised Systems Exploiting Latency Analysis

In-line Test of Synthesised Systems Exploiting Latency Analysis
In-line Test of Synthesised Systems Exploiting Latency Analysis
During normal operation, there are periods of time in which units in a digital system (adders, multipliers etc.) are inactive, i.e. are not processing any useful data. These ?latent periods? may be exploited to continually perform sets of unit tests, thus providing a dynamic indication of the healthiness of the system with little or no effect on its performance. This paper details an analysis technique for identifying and quantifying these latent periods by modelling the flow of control through the system as a Markov chain, which takes into account branching and feedback in the controller. The resulting data describes the distribution of latent periods in an entire design, and, given a testing requirement in the form of a minimum number of (latent) cycles required to perform a test, provides a figure for how often and to what extent a particular unit may be tested during normal operation. This analysis is utilised to investigate the impact particular optimisation strategies have on the distribution of latent periods, in a number of synthesised benchmark designs. These results are further developed to demonstrate how a knowledge of the latent period distribution can be used to direct the synthesis process and lead to a substantial improvement in the distribution of latent periods, whilst not over adversely affecting other design aspects, particularly the area.
Williams, A.C.
24f37520-cb05-45ba-80da-cc4d0211722d
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Williams, A.C.
24f37520-cb05-45ba-80da-cc4d0211722d
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Williams, A.C., Brown, A.D. and Zwolinski, M. (2000) In-line Test of Synthesised Systems Exploiting Latency Analysis

Record type: Other

Abstract

During normal operation, there are periods of time in which units in a digital system (adders, multipliers etc.) are inactive, i.e. are not processing any useful data. These ?latent periods? may be exploited to continually perform sets of unit tests, thus providing a dynamic indication of the healthiness of the system with little or no effect on its performance. This paper details an analysis technique for identifying and quantifying these latent periods by modelling the flow of control through the system as a Markov chain, which takes into account branching and feedback in the controller. The resulting data describes the distribution of latent periods in an entire design, and, given a testing requirement in the form of a minimum number of (latent) cycles required to perform a test, provides a figure for how often and to what extent a particular unit may be tested during normal operation. This analysis is utilised to investigate the impact particular optimisation strategies have on the distribution of latent periods, in a number of synthesised benchmark designs. These results are further developed to demonstrate how a knowledge of the latent period distribution can be used to direct the synthesis process and lead to a substantial improvement in the distribution of latent periods, whilst not over adversely affecting other design aspects, particularly the area.

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More information

Published date: January 2000
Organisations: EEE

Identifiers

Local EPrints ID: 252957
URI: http://eprints.soton.ac.uk/id/eprint/252957
PURE UUID: 6f0839a5-b7b9-44b3-bef6-e26bd2aa1708
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 12 Apr 2000
Last modified: 18 Jul 2017 10:00

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Contributors

Author: A.C. Williams
Author: A.D. Brown
Author: M. Zwolinski ORCID iD

University divisions

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