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A robust analogue interface system for submicron video DSP

A robust analogue interface system for submicron video DSP
A robust analogue interface system for submicron video DSP
This paper describes the front-end architecture for a fully integrated low-voltage CMOS video DSP function, including AGC, equalization, clamping, sync, and A/D conversion. With multiple clock domains and many high-activity pads, the large digital section of the IC generates high levels of substrate and power line noise, which cannot be avoided with guiet period sampling. The analog section is therefore designed to minimize the injected noise by other circuit techniques. The system maximizes the available dynamic range in the 3.3-V supply, with several high-bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the input amplifier, hence reducing amplification of unwanted dc components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5-um CMOS, and operates from a single 3.3-V supply.
0018-9200
1076-1081
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Duffee, R.
2951b772-fef8-4cdc-b058-9a5f867e6553
Bramwell, S.
5c58d8c4-35c7-4ade-874b-c0805748c566
Rijns, H.
56fe8e75-520d-414a-9a47-fa1285ba7823
James, S.
0c110caf-eac1-46cd-99e6-819c3ff58c96
Tijou, J.
a879d513-2eff-4aa4-a7c5-1b326ea8bdef
van der Weide, G.
52fa3a31-1da0-4c83-a68c-6e1972f619c7
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Duffee, R.
2951b772-fef8-4cdc-b058-9a5f867e6553
Bramwell, S.
5c58d8c4-35c7-4ade-874b-c0805748c566
Rijns, H.
56fe8e75-520d-414a-9a47-fa1285ba7823
James, S.
0c110caf-eac1-46cd-99e6-819c3ff58c96
Tijou, J.
a879d513-2eff-4aa4-a7c5-1b326ea8bdef
van der Weide, G.
52fa3a31-1da0-4c83-a68c-6e1972f619c7

Redman-White, W., Duffee, R., Bramwell, S., Rijns, H., James, S., Tijou, J. and van der Weide, G. (1998) A robust analogue interface system for submicron video DSP. IEEE Journal of Solid State Circuits, 33 (7), 1076-1081.

Record type: Article

Abstract

This paper describes the front-end architecture for a fully integrated low-voltage CMOS video DSP function, including AGC, equalization, clamping, sync, and A/D conversion. With multiple clock domains and many high-activity pads, the large digital section of the IC generates high levels of substrate and power line noise, which cannot be avoided with guiet period sampling. The analog section is therefore designed to minimize the injected noise by other circuit techniques. The system maximizes the available dynamic range in the 3.3-V supply, with several high-bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the input amplifier, hence reducing amplification of unwanted dc components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5-um CMOS, and operates from a single 3.3-V supply.

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More information

Published date: July 1998
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 253301
URI: https://eprints.soton.ac.uk/id/eprint/253301
ISSN: 0018-9200
PURE UUID: 6c308830-2f9b-4539-8887-7278a8966157

Catalogue record

Date deposited: 09 Sep 2004
Last modified: 16 Jul 2019 23:05

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