Characterisation of layout dependent thermal coupling in SOI CMOS current mirrors
Characterisation of layout dependent thermal coupling in SOI CMOS current mirrors
A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 µm SOI CMOS technology, with devices separated by as much as 20 µm. Measurements were verified by electrothermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies.
2227-2232
Tenbroek, B. M.
321ed915-008d-4218-9564-57e061886804
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Lee, M. S. L.
6460a2db-498f-49de-b52e-9c134b9cf54d
Bunyan, R. J. T.
f87a3069-9adc-4e66-93ab-858ebb39045b
Uren, M. J.
98cd13fc-b6fa-4126-8ef3-f5fc8be04710
Brunson, K. M.
7063d0f7-608e-4f9f-beb6-5002d29bc07a
December 1996
Tenbroek, B. M.
321ed915-008d-4218-9564-57e061886804
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Lee, M. S. L.
6460a2db-498f-49de-b52e-9c134b9cf54d
Bunyan, R. J. T.
f87a3069-9adc-4e66-93ab-858ebb39045b
Uren, M. J.
98cd13fc-b6fa-4126-8ef3-f5fc8be04710
Brunson, K. M.
7063d0f7-608e-4f9f-beb6-5002d29bc07a
Tenbroek, B. M., Redman-White, W., Lee, M. S. L., Bunyan, R. J. T., Uren, M. J. and Brunson, K. M.
(1996)
Characterisation of layout dependent thermal coupling in SOI CMOS current mirrors.
IEEE Transactions on Electron Devices, 43 (12), .
Abstract
A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 µm SOI CMOS technology, with devices separated by as much as 20 µm. Measurements were verified by electrothermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies.
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Published date: December 1996
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 253305
URI: http://eprints.soton.ac.uk/id/eprint/253305
PURE UUID: 41a06f78-bab7-4250-be3c-57b3bcec181e
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Date deposited: 09 Sep 2004
Last modified: 10 Dec 2021 20:32
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Contributors
Author:
B. M. Tenbroek
Author:
W. Redman-White
Author:
M. S. L. Lee
Author:
R. J. T. Bunyan
Author:
M. J. Uren
Author:
K. M. Brunson
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