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Characterisation of layout dependent thermal coupling in SOI CMOS current mirrors

Tenbroek, B. M., Redman-White, W., Lee, M. S. L., Bunyan, R. J. T., Uren, M. J. and Brunson, K. M. (1996) Characterisation of layout dependent thermal coupling in SOI CMOS current mirrors IEEE Transactions on Electron Devices, 43, (12), pp. 2227-2232.

Record type: Article


A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 um SOI CMOS technology, with devices separated by as much as 20 um. Measurements were verified by eletrothermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies.

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Published date: December 1996
Organisations: Nanoelectronics and Nanotechnology


Local EPrints ID: 253305
PURE UUID: 41a06f78-bab7-4250-be3c-57b3bcec181e

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Date deposited: 09 Sep 2004
Last modified: 18 Jul 2017 09:59

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Author: B. M. Tenbroek
Author: W. Redman-White
Author: M. S. L. Lee
Author: R. J. T. Bunyan
Author: M. J. Uren
Author: K. M. Brunson

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