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Modified Isolation Rings for Parallel Test Access in Core Based SoC

Gonciari, Paul T. and Al-Hashimi, Bashir M. (2000) Modified Isolation Rings for Parallel Test Access in Core Based SoC At IEE System on a Chip Workshop. , 10/1-10/4.

Record type: Conference or Workshop Item (Other)


One of the major issues in implementing core-based systems on a chip (SoC) is testing of cores. This paper presents a method to add parallel test access to cores within the SoC for speeding up the system testing time. This involves the introduction of multiple insertion and extraction points in the existing isolation ring of the core and performing the functions of shifting and bypassing simultaneously. To compute the gain in overall testing time ring parameters are introduced and an example demonstrating the efficiency of the proposed method is given.

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Published date: September 2000
Venue - Dates: IEE System on a Chip Workshop, 2000-09-01
Organisations: Electronic & Software Systems


Local EPrints ID: 253759
PURE UUID: b03776d7-2a90-4c17-8267-5454bffd3e64

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Date deposited: 29 May 2001
Last modified: 18 Jul 2017 09:56

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Author: Paul T. Gonciari

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