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A VHDL Behavioural Synthesis System Featuring Simultaneous Optimisation of Dynamic Power, Area and Delay

A VHDL Behavioural Synthesis System Featuring Simultaneous Optimisation of Dynamic Power, Area and Delay
A VHDL Behavioural Synthesis System Featuring Simultaneous Optimisation of Dynamic Power, Area and Delay
Power dissipation has become one of the main concerns of the design industry today. Methods for reducing power consumption tend, however, to be used in an ad-hoc manner. This paper details the incorporation of a power optimisation criterion within the MOODS behavioural synthesis system which features an integrated incremental power estimation capability enabling the system to optimise a design based on independent, user-specified objectives for final area, delay, clock speed, and power consumption. The tool also incorporates a number of architectural features specifically targeted at reducing power which can be included automatically within any given design during synthesis. The resulting system has shown itself to be capable of reducing the energy consumption of a range of benchmark designs by between 3.5 and 7.0 times.
23-30
Williams, A.C.
24f37520-cb05-45ba-80da-cc4d0211722d
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Williams, A.C.
24f37520-cb05-45ba-80da-cc4d0211722d
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Williams, A.C., Brown, A.D. and Zwolinski, M. (2000) A VHDL Behavioural Synthesis System Featuring Simultaneous Optimisation of Dynamic Power, Area and Delay , pp. 23-30.

Record type: Conference or Workshop Item (Other)

Abstract

Power dissipation has become one of the main concerns of the design industry today. Methods for reducing power consumption tend, however, to be used in an ad-hoc manner. This paper details the incorporation of a power optimisation criterion within the MOODS behavioural synthesis system which features an integrated incremental power estimation capability enabling the system to optimise a design based on independent, user-specified objectives for final area, delay, clock speed, and power consumption. The tool also incorporates a number of architectural features specifically targeted at reducing power which can be included automatically within any given design during synthesis. The resulting system has shown itself to be capable of reducing the energy consumption of a range of benchmark designs by between 3.5 and 7.0 times.

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More information

Published date: September 2000
Additional Information: Organisation: Forum on Design Languages 2000 (FDL 2000)
Organisations: EEE

Identifiers

Local EPrints ID: 254053
URI: http://eprints.soton.ac.uk/id/eprint/254053
PURE UUID: 923f7e64-65ff-49aa-bf01-1d7568492571
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 05 Jul 2001
Last modified: 18 Jul 2017 09:54

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Contributors

Author: A.C. Williams
Author: A.D. Brown
Author: M. Zwolinski ORCID iD

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