A VHDL Behavioural Synthesis System with Floating Point Support
A VHDL Behavioural Synthesis System with Floating Point Support
This paper describes an enhancement to the MOODS (Multiple Objective Optimisation in Data and control path Synthesis) behavioural VHDL synthesis system to support the processing of designs containing floating-point (and complex) arithmetic. In particular, the development of a floating-point module library and a floating-point optimiser capable of making strategic decisions about the high level binding of each floating-point operation in a way that meets the users pre-defined goal. The floating-point modules are based around either iterative generating techniques or lookup tables; either way, the scope of optimisation is considerable, especially when targeting limited architectures such as FPGAs.
31-36
Baidas, Z.A.
1a40da58-6331-4e2a-908c-6dcecc6fbf42
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Williams, A.C.
4c566cf2-8942-410b-9741-eb4a90f7125f
September 2000
Baidas, Z.A.
1a40da58-6331-4e2a-908c-6dcecc6fbf42
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Williams, A.C.
4c566cf2-8942-410b-9741-eb4a90f7125f
Baidas, Z.A., Brown, A.D. and Williams, A.C.
(2000)
A VHDL Behavioural Synthesis System with Floating Point Support.
Forum on Design Languages 2000 (FDL 2000), Tübingen.
04 - 08 Sep 2000.
.
Record type:
Conference or Workshop Item
(Paper)
Abstract
This paper describes an enhancement to the MOODS (Multiple Objective Optimisation in Data and control path Synthesis) behavioural VHDL synthesis system to support the processing of designs containing floating-point (and complex) arithmetic. In particular, the development of a floating-point module library and a floating-point optimiser capable of making strategic decisions about the high level binding of each floating-point operation in a way that meets the users pre-defined goal. The floating-point modules are based around either iterative generating techniques or lookup tables; either way, the scope of optimisation is considerable, especially when targeting limited architectures such as FPGAs.
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Published date: September 2000
Venue - Dates:
Forum on Design Languages 2000 (FDL 2000), Tübingen, 2000-09-04 - 2000-09-08
Organisations:
EEE
Identifiers
Local EPrints ID: 254055
URI: http://eprints.soton.ac.uk/id/eprint/254055
PURE UUID: f7a753f0-e851-4421-849d-75e1a777bc43
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Date deposited: 05 Jul 2001
Last modified: 16 Nov 2022 17:36
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Contributors
Author:
Z.A. Baidas
Author:
A.D. Brown
Author:
A.C. Williams
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