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A VHDL Behavioural Synthesis System with Floating Point Support

Baidas, Z.A., Brown, A.D. and Williams, A.C. (2000) A VHDL Behavioural Synthesis System with Floating Point Support At Forum on Design Languages 2000 (FDL 2000). 04 - 08 Sep 2000. , pp. 31-36.

Record type: Conference or Workshop Item (Paper)


This paper describes an enhancement to the MOODS (Multiple Objective Optimisation in Data and control path Synthesis) behavioural VHDL synthesis system to support the processing of designs containing floating-point (and complex) arithmetic. In particular, the development of a floating-point module library and a floating-point optimiser capable of making strategic decisions about the high level binding of each floating-point operation in a way that meets the users pre-defined goal. The floating-point modules are based around either iterative generating techniques or lookup tables; either way, the scope of optimisation is considerable, especially when targeting limited architectures such as FPGAs.

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Published date: September 2000
Venue - Dates: Forum on Design Languages 2000 (FDL 2000), 2000-09-04 - 2000-09-08
Organisations: EEE


Local EPrints ID: 254055
PURE UUID: f7a753f0-e851-4421-849d-75e1a777bc43

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Date deposited: 05 Jul 2001
Last modified: 18 Jul 2017 09:54

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Author: Z.A. Baidas
Author: A.D. Brown
Author: A.C. Williams

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