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Low Power Testing of Digital ICs: Overview

Low Power Testing of Digital ICs: Overview
Low Power Testing of Digital ICs: Overview
This paper presents an overview of low power testing of digital ICs and show why traditional DFT techniques are not suitable for low power VLSI circuits with the help of examples. The paper reviews some of the recently proposed work for lowering power during test including the work at southampton in terms of scan based and RTL datapath power disspation.
3-4
Al-hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871
Al-hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871

Al-hashimi, Bashir and Nicolici, Nicola (2000) Low Power Testing of Digital ICs: Overview , pp. 3-4.

Record type: Conference or Workshop Item (Other)

Abstract

This paper presents an overview of low power testing of digital ICs and show why traditional DFT techniques are not suitable for low power VLSI circuits with the help of examples. The paper reviews some of the recently proposed work for lowering power during test including the work at southampton in terms of scan based and RTL datapath power disspation.

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More information

Published date: October 2000
Additional Information: Organisation: University of Manchester Address: University of Manchester
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 254133
URI: http://eprints.soton.ac.uk/id/eprint/254133
PURE UUID: b74ad5e8-0b6e-4820-afc4-23a0b5ea7319

Catalogue record

Date deposited: 29 May 2001
Last modified: 18 Jul 2017 09:54

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Contributors

Author: Nicola Nicolici

University divisions

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