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SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation

SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation
SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation
SiGe device islands have been synthesised by Ge+ ion implantation of doses of 0.45 x 1016Ge+/cm2 to 4.05 x1016Ge+/cm2 at 100keV or 200keV into patterned (100) bulk silicon wafers. The control of 'mask edge defects' and 'end of range' defects has been achieved by applying Si+ post-amorphisation, where the ions are implanted into a wider window, and by using solid phase epitaxial regrowth. Defect free SiGe alloy islands with a peak Ge concentration of ~6at% and minority carrier generation lifetimes comparible to bulk silicon (~ms) have been successfully produced. The integration of this synthesis process into CMOS and bipolar technologies is discussed. Realization of shallower islands, with dimensions more consistent with future generations of advanced devices and with higher Ge contents, is in hand.
Graoui, H.
d1fa192c-3cd2-4ede-9de1-b86efec09b9c
Nejim, A.
844d60f1-e438-4ffe-a309-47245b9000f0
Hemment, P.L.F.
198ac06e-1c48-4422-a3a4-de753f22dec3
Riley, L.
8f4585dc-7bec-40c5-9ca6-82a026d8613b
Mitchell, M.
79fd3d5f-d070-4512-b583-2fbdb4519fad
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Graoui, H.
d1fa192c-3cd2-4ede-9de1-b86efec09b9c
Nejim, A.
844d60f1-e438-4ffe-a309-47245b9000f0
Hemment, P.L.F.
198ac06e-1c48-4422-a3a4-de753f22dec3
Riley, L.
8f4585dc-7bec-40c5-9ca6-82a026d8613b
Mitchell, M.
79fd3d5f-d070-4512-b583-2fbdb4519fad
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Graoui, H., Nejim, A., Hemment, P.L.F., Riley, L., Mitchell, M. and Ashburn, P. (2000) SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation. Proceedings of Ion Implantation Technology Conference.

Record type: Conference or Workshop Item (Other)

Abstract

SiGe device islands have been synthesised by Ge+ ion implantation of doses of 0.45 x 1016Ge+/cm2 to 4.05 x1016Ge+/cm2 at 100keV or 200keV into patterned (100) bulk silicon wafers. The control of 'mask edge defects' and 'end of range' defects has been achieved by applying Si+ post-amorphisation, where the ions are implanted into a wider window, and by using solid phase epitaxial regrowth. Defect free SiGe alloy islands with a peak Ge concentration of ~6at% and minority carrier generation lifetimes comparible to bulk silicon (~ms) have been successfully produced. The integration of this synthesis process into CMOS and bipolar technologies is discussed. Realization of shallower islands, with dimensions more consistent with future generations of advanced devices and with higher Ge contents, is in hand.

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More information

Published date: September 2000
Venue - Dates: Proceedings of Ion Implantation Technology Conference, 2000-09-01
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 255699
URI: http://eprints.soton.ac.uk/id/eprint/255699
PURE UUID: e730f327-65b5-4770-aa97-ce3c0d63d015

Catalogue record

Date deposited: 02 Apr 2001
Last modified: 17 Jul 2019 22:34

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