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SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation

Graoui, H., Nejim, A., Hemment, P.L.F., Riley, L., Mitchell, M. and Ashburn, P. (2000) SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation At Proceedings of Ion Implantation Technology Conference.

Record type: Conference or Workshop Item (Other)


SiGe device islands have been synthesised by Ge+ ion implantation of doses of 0.45 x 1016Ge+/cm2 to 4.05 x1016Ge+/cm2 at 100keV or 200keV into patterned (100) bulk silicon wafers. The control of 'mask edge defects' and 'end of range' defects has been achieved by applying Si+ post-amorphisation, where the ions are implanted into a wider window, and by using solid phase epitaxial regrowth. Defect free SiGe alloy islands with a peak Ge concentration of ~6at% and minority carrier generation lifetimes comparible to bulk silicon (~ms) have been successfully produced. The integration of this synthesis process into CMOS and bipolar technologies is discussed. Realization of shallower islands, with dimensions more consistent with future generations of advanced devices and with higher Ge contents, is in hand.

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Published date: September 2000
Venue - Dates: Proceedings of Ion Implantation Technology Conference, 2000-09-01
Organisations: Nanoelectronics and Nanotechnology


Local EPrints ID: 255699
PURE UUID: e730f327-65b5-4770-aa97-ce3c0d63d015

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Date deposited: 02 Apr 2001
Last modified: 18 Jul 2017 09:51

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Author: H. Graoui
Author: A. Nejim
Author: P.L.F. Hemment
Author: L. Riley
Author: M. Mitchell
Author: P. Ashburn

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