Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees

Asensi, G.D., Kazmierski, T.J. and Merino, R.R. (2000) Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees. Electronics Letters, 36 (20), 1680-1682. (doi:10.1049/el:20001202).

Abstract

A technique of translating high-level analogue dynamic system behavioural models from VHDL-AMS parse trees into circuit-level netlists is described. The primary application of this work is automatic synthesis of general analogue dynamic systems with feedback. The technique is demonstrated with a practical example of Lorenz's chaos system synthesis.

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