Architctural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees


Asensi, G.D., Kazmierski, T.J. and Merino, R.R. (2000) Architctural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees Electronics Letters, v 36,, (20), pp. 1680-1682.

Download

Full text not available from this repository.

Item Type: Article
ISSNs: 0013-5194 (print)
Organisations: EEE
ePrint ID: 255719
Date :
Date Event
September 2000Published
Date Deposited: 11 Apr 2001
Last Modified: 17 Apr 2017 23:14
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/255719

Actions (login required)

View Item View Item