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Architctural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees

Asensi, G.D., Kazmierski, T.J. and Merino, R.R. (2000) Architctural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees Electronics Letters, v 36,, (20), pp. 1680-1682.

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Published date: September 2000
Organisations: EEE

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Local EPrints ID: 255719
URI: http://eprints.soton.ac.uk/id/eprint/255719
ISSN: 0013-5194
PURE UUID: 0fe88bd5-eb20-44e6-85ee-2dee8d07b09b

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Date deposited: 11 Apr 2001
Last modified: 18 Jul 2017 09:51

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Contributors

Author: G.D. Asensi
Author: T.J. Kazmierski
Author: R.R. Merino

University divisions

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