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A Technique for Transparent Fault Injection and Simulation in VHDL

Zwolinski, M. (2000) A Technique for Transparent Fault Injection and Simulation in VHDL At Small System Simulation Symposium (SSSS).

Record type: Conference or Workshop Item (Other)


A technique is described for the automatic insertion of fault models into VHDL gate models, using shared variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. A method for automatic sequential fault simulation is further demonstrated.

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Published date: September 2000
Venue - Dates: Small System Simulation Symposium (SSSS), 2000-09-01
Organisations: EEE


Local EPrints ID: 255729
PURE UUID: bd3ccb89-7cdb-4ba0-a2b4-8c402cadb9d1
ORCID for M. Zwolinski: ORCID iD

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Date deposited: 17 Apr 2001
Last modified: 18 Jul 2017 09:51

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Author: M. Zwolinski ORCID iD

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