A Technique for Transparent Fault Injection and Simulation in VHDL
At Small System Simulation Symposium (SSSS).
Full text not available from this repository.
A technique is described for the automatic insertion of fault models into VHDL gate models, using shared variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. A method for automatic sequential fault simulation is further demonstrated.
Conference or Workshop Item
|Venue - Dates:
||Small System Simulation Symposium (SSSS), 2000-09-01
||17 Apr 2001
||17 Apr 2017 23:14
|Further Information:||Google Scholar|
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