A novel deep submicron elevated source/drain MOSFET

Waite, A.M., Kubicek, S., Howard, D., Caymax, M., DeMeyer, K. and Evans, A.G.R. (1998) A novel deep submicron elevated source/drain MOSFET. In 28th European Solid-State Device Research Conference. IEEE. 4 pp .

Abstract

In this paper we report on the electrical characteristics of a novel elevated source/ drain MOS-FET. The elevated structures are created by growing a layer of selective epitaxial silicon in the source and drain regions of the MOSFET. The selective epitaxial process does not suffer from faceting at the edges of the epitaxial silicon layers, and the thermal budget of the process is compatible with deep sub-micron CMOS. The process uses a disposable cap on top of the gate polysilicon to prevent epitaxial silicon growth on the polysilicon. This cap is later removed to enable salicidation of the gate. Electrical results are presented which show that our new elevated PMOS devices give superior saturation current drive and contribute to a higher ring oscillator speed than conventional non elevated MOSFETs.

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