SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide

Sidek, R M, Straube, U N, Waite, A M, Evans, A G R, Parry, C, Phillips, P, Whall, T E and Parker, E H C (2000) SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide. Semiconductor Science and Technology, 15 (2), 135-138. (doi:10.1088/0268-1242/15/2/310).

Abstract

An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer, The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.

This record has no associated files available for download.

Contributors

Download statistics