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Temporal Logic Model Checking of CSP: Tools and Techniques

Record type: Conference or Workshop Item (Other)

We study the possibility of doing LTL model checking on CSP specifications in the context of refinement. We present a technique to perform LTL model checking of CSP processes using refinement checking in general and the FDR tool in particular. We present a tool which automates the translation process from LTL model checking to CSP refinement. Also, if time permits, we will present another tool which uses latest generation Prolog technology to symbolically animate, compile, and model check CSP specifications.

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Citation

Leuschel, Michael, Wolton, Ivan, Massart, Thierry and Adhianto, Laksono, (2001) Temporal Logic Model Checking of CSP: Tools and Techniques Nowak, David (ed.) At Proceedings of the Workshop on Automated Verification of Critical Systems (AVOCS'01).

More information

Published date: April 2001
Additional Information: Technical Report.
Venue - Dates: Proceedings of the Workshop on Automated Verification of Critical Systems (AVOCS'01), 2001-04-01
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 255930
URI: http://eprints.soton.ac.uk/id/eprint/255930
PURE UUID: 7902ad21-f79f-4b7e-9c82-584acc3d8377

Catalogue record

Date deposited: 15 Jun 2001
Last modified: 18 Jul 2017 09:50

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Contributors

Author: Michael Leuschel
Author: Ivan Wolton
Author: Thierry Massart
Author: Laksono Adhianto
Editor: David Nowak

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