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Tackling Test Trade-offs for BIST RTL Data Paths: BIST Area Overhead, Test Application Time and Power Dissipation

Tackling Test Trade-offs for BIST RTL Data Paths: BIST Area Overhead, Test Application Time and Power Dissipation
Tackling Test Trade-offs for BIST RTL Data Paths: BIST Area Overhead, Test Application Time and Power Dissipation
Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation. Using a complex validation flow and experimental data for over 30,000 testable data paths, it is shown how test application time decreases asymptotically when increasing power constraints. Further, it is experimentally demonstrated why power conscious test synthesis and test scheduling algorithms are required due to large variations in useless power dissipation as test application time decreases. Finally, while previous research has outlined that test application time decreases as BIST area overhead increases, this paper shows that in order to reach high quality solutions in terms of test application time and BIST area overhead under given power constraints, a three dimensional design space needs to be explored.
Nicolici, N.
9be70b5e-becc-4ec4-a564-14758ef4f03c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, N.
9be70b5e-becc-4ec4-a564-14758ef4f03c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Nicolici, N. and Al-Hashimi, B.M. (2001) Tackling Test Trade-offs for BIST RTL Data Paths: BIST Area Overhead, Test Application Time and Power Dissipation

Record type: Conference or Workshop Item (Other)

Abstract

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation. Using a complex validation flow and experimental data for over 30,000 testable data paths, it is shown how test application time decreases asymptotically when increasing power constraints. Further, it is experimentally demonstrated why power conscious test synthesis and test scheduling algorithms are required due to large variations in useless power dissipation as test application time decreases. Finally, while previous research has outlined that test application time decreases as BIST area overhead increases, this paper shows that in order to reach high quality solutions in terms of test application time and BIST area overhead under given power constraints, a three dimensional design space needs to be explored.

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More information

Published date: October 2001
Additional Information: Organisation: IEEE Computer Society
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 255957
URI: http://eprints.soton.ac.uk/id/eprint/255957
PURE UUID: ec0d40cf-2e12-4c8e-a595-26f647ebfc21

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Date deposited: 29 Jun 2001
Last modified: 18 Jul 2017 09:50

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Contributors

Author: N. Nicolici
Author: B.M. Al-Hashimi

University divisions

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