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Si/Si0.64Ge0.36/Si pMOSFETs with Enhanced Voltage Gain and Low 1/f Noise

Prest, M. J., Palmer, M. J., Braithwaite, G., Grasby, T. J., Phillips, P. J., Mironov, O. A., Parker, E. H. C., Whall, T. E., Waite, A. M. and Evans, A. G. R. (2001) Si/Si0.64Ge0.36/Si pMOSFETs with Enhanced Voltage Gain and Low 1/f Noise

Record type: Other


Si/Si0.64Fe0.36/Si p MOSFETs with written gate lengths in the range 0.5mu micron to 10mu micron have been fabricated in a reduced thermal budget variant of a standard CMOS process. The devices exhibit enhanced maximum voltage-gains and reduced 1/f noise as compared to silicon controls.

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Published date: 2001
Additional Information: Organisation: ESSDERC 2001
Organisations: Nanoelectronics and Nanotechnology


Local EPrints ID: 256168
PURE UUID: 9bbed223-aed1-4489-9ed6-d70a74a2eb62

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Date deposited: 10 Dec 2001
Last modified: 18 Jul 2017 09:48

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Author: M. J. Prest
Author: M. J. Palmer
Author: G. Braithwaite
Author: T. J. Grasby
Author: P. J. Phillips
Author: O. A. Mironov
Author: E. H. C. Parker
Author: T. E. Whall
Author: A. M. Waite
Author: A. G. R. Evans

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