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Faults and fault effects in NMOS circuits - impact on design for testability

Faults and fault effects in NMOS circuits - impact on design for testability
Faults and fault effects in NMOS circuits - impact on design for testability
VLSI circuits currently being designed are so complex that it is now extremely difficult to test them adequately to determine whether or not they have been processed correctly. Design for testability (DFT) techniques are often used in an attempt to ease this problem by identifying and redesigning potentially 'difficult-to-test' parts of the circuits. The 'testability' of the circuit is usually evaluated in terms of the stuck-at fault model. However, there have been growing doubts over the ability of this model to cover certain common faults that can occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simulations of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellable as 'stuck' nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined. Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. We therefore conclude with a discussion of ad hoc 'physical design for testability' techniques that exploit current understanding of the relation between MOS faults and their fault effects.
82-89
Burgess, N.
2e290a85-7733-415b-a97d-2157494ffaf6
Damper, R.I.
6e0e7fdc-57ec-44d4-bc0f-029d17ba441d
Shaw, S.J.
9654cc5a-8226-42e7-aa40-a19e5da5f4fb
Wilkins, D.R.J.
3157ef0d-65ba-4568-b9cc-d5d10a74b2be
Burgess, N.
2e290a85-7733-415b-a97d-2157494ffaf6
Damper, R.I.
6e0e7fdc-57ec-44d4-bc0f-029d17ba441d
Shaw, S.J.
9654cc5a-8226-42e7-aa40-a19e5da5f4fb
Wilkins, D.R.J.
3157ef0d-65ba-4568-b9cc-d5d10a74b2be

Burgess, N., Damper, R.I., Shaw, S.J. and Wilkins, D.R.J. (1985) Faults and fault effects in NMOS circuits - impact on design for testability. IEE Proceedings G - Electronic Circuits and Systems, 132 (3), 82-89. (doi:10.1049/ip-g-1.1985.0019).

Record type: Article

Abstract

VLSI circuits currently being designed are so complex that it is now extremely difficult to test them adequately to determine whether or not they have been processed correctly. Design for testability (DFT) techniques are often used in an attempt to ease this problem by identifying and redesigning potentially 'difficult-to-test' parts of the circuits. The 'testability' of the circuit is usually evaluated in terms of the stuck-at fault model. However, there have been growing doubts over the ability of this model to cover certain common faults that can occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simulations of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellable as 'stuck' nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined. Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. We therefore conclude with a discussion of ad hoc 'physical design for testability' techniques that exploit current understanding of the relation between MOS faults and their fault effects.

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Published date: June 1985
Organisations: Southampton Wireless Group

Identifiers

Local EPrints ID: 256204
URI: https://eprints.soton.ac.uk/id/eprint/256204
PURE UUID: a3498bd6-4803-474d-a5a3-157bbbf2f333

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Date deposited: 27 Dec 2001
Last modified: 12 Nov 2018 17:31

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Contributors

Author: N. Burgess
Author: R.I. Damper
Author: S.J. Shaw
Author: D.R.J. Wilkins

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