Faults effects in MOS circuits and their implications for digital circuit testing
Faults effects in MOS circuits and their implications for digital circuit testing
83-91
Burgess, N.
2e290a85-7733-415b-a97d-2157494ffaf6
Wilkins, D. R. J.
1907f83e-31b3-4389-a73d-6f71745165ff
Damper, R. I.
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Shaw, S. J.
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1985
Burgess, N.
2e290a85-7733-415b-a97d-2157494ffaf6
Wilkins, D. R. J.
1907f83e-31b3-4389-a73d-6f71745165ff
Damper, R. I.
6e0e7fdc-57ec-44d4-bc0f-029d17ba441d
Shaw, S. J.
fca53a76-84c1-45a2-8754-897c8afff5cf
Burgess, N., Wilkins, D. R. J., Damper, R. I. and Shaw, S. J.
(1985)
Faults effects in MOS circuits and their implications for digital circuit testing.
IEE Conference Publication No. 232, Electronic Design Automation (EDA'84).
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Published date: 1985
Additional Information:
Address: Warwick, UK
Venue - Dates:
IEE Conference Publication No. 232, Electronic Design Automation (EDA'84), 1985-01-01
Organisations:
Southampton Wireless Group
Identifiers
Local EPrints ID: 256219
URI: http://eprints.soton.ac.uk/id/eprint/256219
PURE UUID: 0e778fee-846e-4a6d-82b9-6f1bc61eba50
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Date deposited: 03 Jan 2002
Last modified: 10 Dec 2021 20:42
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Contributors
Author:
N. Burgess
Author:
D. R. J. Wilkins
Author:
R. I. Damper
Author:
S. J. Shaw
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