Algorithmic Complexity, SPeed and Architectural Parallelism in Low data-rate Visual Communications
Algorithmic Complexity, SPeed and Architectural Parallelism in Low data-rate Visual Communications
Consideration is given to the tradeoff between algorithmic complexity and processing speed in primitive extraction for low data-rate visual communication. Initial experiments with serially-implemented algorithms on an MC68000 processor indicated the need for a high degree of parallelism in order to meet the requirements of real-time, moving-picture data rates. However, insight gained by trials on CLIP4, which typically showed speed gains of 40%, points to window-based architectures implemented using look-up tables.
185-191
Martinez, K.
5f711898-20fc-410e-a007-837d8c57cb18
Pearson, D. E.
f406687c-5dae-4a78-af33-47288300cf87
April 1985
Martinez, K.
5f711898-20fc-410e-a007-837d8c57cb18
Pearson, D. E.
f406687c-5dae-4a78-af33-47288300cf87
Martinez, K. and Pearson, D. E.
(1985)
Algorithmic Complexity, SPeed and Architectural Parallelism in Low data-rate Visual Communications.
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Conference or Workshop Item
(Other)
Abstract
Consideration is given to the tradeoff between algorithmic complexity and processing speed in primitive extraction for low data-rate visual communication. Initial experiments with serially-implemented algorithms on an MC68000 processor indicated the need for a high degree of parallelism in order to meet the requirements of real-time, moving-picture data rates. However, insight gained by trials on CLIP4, which typically showed speed gains of 40%, points to window-based architectures implemented using look-up tables.
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Published date: April 1985
Organisations:
Web & Internet Science
Identifiers
Local EPrints ID: 256303
URI: http://eprints.soton.ac.uk/id/eprint/256303
PURE UUID: aa06b850-3f03-4e53-b631-e76159ba154c
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Date deposited: 04 Feb 2002
Last modified: 11 Dec 2021 03:15
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Contributors
Author:
K. Martinez
Author:
D. E. Pearson
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