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Simultaneous Reduction in Volume of Test Data and Power Dissipation for Systems-on-a-Chip

Rosinger, Paul, Gonciari, Theo, Al-Hashimi, Bashir and Nicolici, Nicola, IEE, None(ed.) (2001) Simultaneous Reduction in Volume of Test Data and Power Dissipation for Systems-on-a-Chip Electronics Letters, 37, (24), pp. 1434-1436.

Record type: Article


This letter investigates the reasons for the current trade-off of test data volume for scan power dissipation in system-on-chip (SOC) testing, understands the conflict between the existing compression method and scan power minimization technique and proves that by using a new compression method this trade-off is unnecessary. When the new compression method is combined with scan reordering savings up to 97% in peak power and 99% in average power, as well as compression ratios of up to 95% are possible.

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Published date: November 2001
Additional Information: Address: London
Organisations: Electronic & Software Systems


Local EPrints ID: 256353
ISSN: 0013-5194
PURE UUID: c0421ee1-a742-442b-9114-188501d8de8e

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Date deposited: 28 Feb 2002
Last modified: 18 Jul 2017 09:47

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Author: Paul Rosinger
Author: Theo Gonciari
Author: Nicola Nicolici
Editor: None IEE

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