Analysing trade-offs in scan power and test data compression for Systems-on-a-chip
Analysing trade-offs in scan power and test data compression for Systems-on-a-chip
This paper investigates the relationship between test data compression and power dissipation during scan testing. Trade-off analysis using ISCAS89 benchmark circuits show that by employing the recently proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can explicitly control the scan power and volume of test data.
Rosinger, P
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Gonciari, P
45064aec-d084-47ea-aa5e-94014ab54fab
Al-Hashimi, B.M
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871
August 2002
Rosinger, P
72888b6b-9095-46e5-93e6-5a9098cac294
Gonciari, P
45064aec-d084-47ea-aa5e-94014ab54fab
Al-Hashimi, B.M
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871
Rosinger, P, Gonciari, P, Al-Hashimi, B.M and Nicolici, Nicola
(2002)
Analysing trade-offs in scan power and test data compression for Systems-on-a-chip.
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Abstract
This paper investigates the relationship between test data compression and power dissipation during scan testing. Trade-off analysis using ISCAS89 benchmark circuits show that by employing the recently proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can explicitly control the scan power and volume of test data.
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More information
Published date: August 2002
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 256510
URI: http://eprints.soton.ac.uk/id/eprint/256510
PURE UUID: ad2f0d9c-2e78-405d-8a65-880d225b5769
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Date deposited: 10 Jun 2002
Last modified: 08 Jan 2022 05:42
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Contributors
Author:
P Rosinger
Author:
P Gonciari
Author:
B.M Al-Hashimi
Author:
Nicola Nicolici
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