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Analysing trade-offs in scan power and test data compression for Systems-on-a-chip

Rosinger, P, Gonciari, P, Al-Hashimi, B.M and Nicolici, Nicola (2002) Analysing trade-offs in scan power and test data compression for Systems-on-a-chip

Record type: Conference or Workshop Item (Other)


This paper investigates the relationship between test data compression and power dissipation during scan testing. Trade-off analysis using ISCAS89 benchmark circuits show that by employing the recently proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can explicitly control the scan power and volume of test data.

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Published date: August 2002
Organisations: Electronic & Software Systems


Local EPrints ID: 256510
PURE UUID: ad2f0d9c-2e78-405d-8a65-880d225b5769

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Date deposited: 10 Jun 2002
Last modified: 18 Jul 2017 09:46

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Author: P Rosinger
Author: P Gonciari
Author: B.M Al-Hashimi
Author: Nicola Nicolici

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