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Automated high level synthesis of hardware building blocks present in ART--based neural networks, from VHDL--AMS descriptions

Automated high level synthesis of hardware building blocks present in ART--based neural networks, from VHDL--AMS descriptions
Automated high level synthesis of hardware building blocks present in ART--based neural networks, from VHDL--AMS descriptions
This contribution presents a VHDL--AMS model from a building block present in multichannel neural network based on the adaptive resonnance theory, and its automated synthesis using VHDL--AMS to hspice netlist translator. This building block shows continous dynamic behaviour, and it is complex enough to check the functionality of our translator. Both simulations, behavioural high level based on the VHDL--AMS model and structural based on SPICE automatically synthesized description, have been done in order to check the matching between the SPICE netlist synthesized againts its VHDL--AMS model.
Lopez, J. A.
a331dcfe-e709-4fe3-afe4-e171b2cf35ac
Asensi, G. D.
f5849307-5b19-4819-beb9-60c4d24857c0
Ruiz, R.
d2191e20-ca34-4da1-aa3a-6d3ec387b8db
Kazmierski, T.J.
a97d7958-40c3-413f-924d-84545216092a
Lopez, J. A.
a331dcfe-e709-4fe3-afe4-e171b2cf35ac
Asensi, G. D.
f5849307-5b19-4819-beb9-60c4d24857c0
Ruiz, R.
d2191e20-ca34-4da1-aa3a-6d3ec387b8db
Kazmierski, T.J.
a97d7958-40c3-413f-924d-84545216092a

Lopez, J. A., Asensi, G. D., Ruiz, R. and Kazmierski, T.J. (2002) Automated high level synthesis of hardware building blocks present in ART--based neural networks, from VHDL--AMS descriptions. Proc. ISCAS'2002.

Record type: Conference or Workshop Item (Other)

Abstract

This contribution presents a VHDL--AMS model from a building block present in multichannel neural network based on the adaptive resonnance theory, and its automated synthesis using VHDL--AMS to hspice netlist translator. This building block shows continous dynamic behaviour, and it is complex enough to check the functionality of our translator. Both simulations, behavioural high level based on the VHDL--AMS model and structural based on SPICE automatically synthesized description, have been done in order to check the matching between the SPICE netlist synthesized againts its VHDL--AMS model.

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More information

Published date: May 2002
Venue - Dates: Proc. ISCAS'2002, 2002-05-01
Organisations: EEE

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Local EPrints ID: 256523
URI: https://eprints.soton.ac.uk/id/eprint/256523
PURE UUID: eea23a2a-8467-423b-a9c2-eff13d8f9b31

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Date deposited: 25 Apr 2002
Last modified: 16 Jul 2019 22:58

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Contributors

Author: J. A. Lopez
Author: G. D. Asensi
Author: R. Ruiz
Author: T.J. Kazmierski

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