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Unified BIST and functional optimisation in behavioural synthesis

Unified BIST and functional optimisation in behavioural synthesis
Unified BIST and functional optimisation in behavioural synthesis
Built In Self Test (BIST) has emerged as a promising solution for increasingly fast and dense VLSI circuits. Traditionally, the testability insertion phase comes after functional logic synthesis and verification in the VLSI design cycle. This creates two separate optimisation processes: functional optimisation and BIST insertion and optimisation. The first deals with functional design behaviour, while the second deals with test behaviour. In behavioural synthesis, considering testability at such a late stage in the design flow limits the efficient design space exploration as it contradicts the design methodology convergence requirements. It can lead to problems such as exceeding chip area, inability to achieve the required throughput, degraded performance, and inability to apply certain test methods efficiently. Unlike earlier work on "BISTing" data paths, we propose a novel method for inserting and optimising BIST structures at an early stage of High Level Synthesis.
Gaur, Manoj Singh
daa3f35d-eb48-4b0a-99e2-3703a88d54a2
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Gaur, Manoj Singh
daa3f35d-eb48-4b0a-99e2-3703a88d54a2
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Gaur, Manoj Singh and Zwolinski, Mark (2002) Unified BIST and functional optimisation in behavioural synthesis

Record type: Other

Abstract

Built In Self Test (BIST) has emerged as a promising solution for increasingly fast and dense VLSI circuits. Traditionally, the testability insertion phase comes after functional logic synthesis and verification in the VLSI design cycle. This creates two separate optimisation processes: functional optimisation and BIST insertion and optimisation. The first deals with functional design behaviour, while the second deals with test behaviour. In behavioural synthesis, considering testability at such a late stage in the design flow limits the efficient design space exploration as it contradicts the design methodology convergence requirements. It can lead to problems such as exceeding chip area, inability to achieve the required throughput, degraded performance, and inability to apply certain test methods efficiently. Unlike earlier work on "BISTing" data paths, we propose a novel method for inserting and optimising BIST structures at an early stage of High Level Synthesis.

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More information

Published date: August 2002
Additional Information: Organisation: IEEE Computer Society Technical Council on Test Technology and VLSI Society of India
Organisations: EEE

Identifiers

Local EPrints ID: 256601
URI: http://eprints.soton.ac.uk/id/eprint/256601
PURE UUID: 8bfa99b0-a88b-475b-92aa-5996c3dc69d7
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 30 May 2002
Last modified: 18 Jul 2017 09:45

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Contributors

Author: Manoj Singh Gaur
Author: Mark Zwolinski ORCID iD

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