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Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits

Nicolici, Nicola and Al-Hashimi, Bashir (2002) Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits , pp. 721-733.

Record type: Conference or Workshop Item (Other)

Abstract

This paper presents a new technique for power minimization during test application in sequential circuits using multiple scan chains. The technique is based on a new design for test architecture and a novel test application strategy which reduces spurious transitions in the circuit under test. To facilitate the reduction of spurious transitions, the proposed design for test architecture is based on classifying scan latches into compatible, incompatible and independent scan latches. Based on their classification, the scan latches are partitioned into multiple scan chains and a single extra test vector associated with each scan chain is computed. A new test application strategy which applies the extra test vector to primary inputs while shifting out test responses for each scan chain, minimizes power dissipation by eliminating the spurious transitions which occur in the combinational part of the circuit. The newly introduced multiple scan chain-based technique does not introduce performance degradation and minimizes clock tree power dissipation with minimal impact on both test area and test data overhead. Unlike previous approaches which are test set dependent and, hence, are not able to handle large circuits due to the complexity of the design space, this paper shows that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time for both small and large test sets. For example, in the case of the benchmark circuit s15850 it takes <600s in computational time and <1 percent in test area and test data overhead to achieve over 80 percent savings in power dissipation.

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More information

Published date: June 2002
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 256610
URI: http://eprints.soton.ac.uk/id/eprint/256610
PURE UUID: 11874054-7a41-40fc-b14d-0927e1b9c913

Catalogue record

Date deposited: 18 Jun 2002
Last modified: 18 Jul 2017 09:44

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Contributors

Author: Nicola Nicolici

University divisions

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