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Low Power Systems-on-Chip

Low Power Systems-on-Chip
Low Power Systems-on-Chip
Editorial Special Issue Power consumption is arguably becoming the most important parameter in electronic portable system design where excess power dissipation can lead to expensive and less reliable systems. Furthermore, advances in silicon technology are enabling entire systems to be fabricated on a single chip, i.e. systems-on-a-chip (SoC). The development of low power devices, circuits, algorithms and architectures, as well as CAD tools, are fundamental for the successful realisation of SoC for wireless communications and portable computing applications. This special issue is devoted to some of the recent advances in low power SoC design and test. The first three papers address SoC power minimisation at the device, circuit and architecture levels. The first paper, by R. Zhang, K. Roy, C. Koh and D. Janes, investigates device structures and interconnect architectures for multi-device-layer integrated SOI circuits. Detailed comparison with single- and double-gate SOI circuits show that multi-device-layer circuits are a viable solution for future low power high performance applications. The second paper, by R. Chang, P. Hung and I Wang, presents a new adiabatic logic called complementary pass-transistor energy recovery logic (CPERL) for low power applications. Power consumption analysis and simulation of inverters and adders based on CPERL show that CPERL circuits consume less power than those designed with NMOS energy recovery logic. The third paper, by S. Osborne, A. Erdogan, T. Arslan and D. Robinson, describes a low power bus encoding architecture targeting industrial SoC platforms. Implementation, power analysis and synthesis of the architecture are discussed and show that by using the proposed architecture a power saving of up to 22% is possible. The next three papers deal with various aspects of low power embedded systems, including energy reduction, modelling and simulation. The fourth paper, by L. Benini, A. Macii and A. Nannarelli, considers a new approach for reducing static code size and instruction fetch energy for cache-based processors. A hardware unit capable of performing on-the-fly decompression is given including its synthesis and energy estimation. The efficiency of the approach is validated using extensive benchmarking. The fifth paper, by M. Dasygenis, N. Kroupis, K. Tatas, A. Argyriou, D. Soudris and A. Thanailakis, presents a framework for designing energy and performance efficient embedded systems with emphasis on data and instruction memories. A number of multimedia examples are given illustrating the capabilities of the framework for optimising the trade-offs between performance and energy consumption. The sixth paper, by R. Muresan and C. Gebotys, describes a new macro-modelling approach for analyzing low-level current dynamics at the instruction and program level for a complex very long instruction word DSP processor core. The approach is validated with real power measurements of a DSP processor core in a VLSI chip. Developing test strategies for SoC is a challenge for a number of reasons including limited access to cores and large volumes of test data. The final paper, by P. Rosinger, P. Gonciari, B. Al-Hashimi and N. Nicolici, studies two important issues in SoC testing: scan power dissipation and volume of test data, discussing the relationship between the two. They show that the embedded core designer has the option of tuning the scan DFT hardware towards given power and test data volume constraints. The guest editors would like to thank Prof. E. Dagless for supporting the development of this special issue and to April Sparks, Linda Meller, Shirley Rossall and Stuart Govan at the IEE for their assistance in producing this issue. We would also like to sincerely thank all the authors for submitting their papers and the reviewers for keeping up with the very tight schedule that allowed us to complete this special issue as planned in less than a year. It is our sincere hope that this special issue will help augment and enhance the growing research and development efforts in low power SoC. Dr. Bashir Al-HashimiProf. Enrico MaciiProf. Kaushick Roy
Al-Hashimi, Bashir
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Macii, Prof. E.
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Roy, Prof. K.
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Al-Hashimi, Bashir
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Macii, Prof. E.
eca14984-9906-44a7-bd18-dde28277db20
Roy, Prof. K.
f68efac1-4775-4434-a7e6-a94da33ca5dc

(2002) Low Power Systems-on-Chip Al-Hashimi, Bashir, Macii, Prof. E. and Roy, Prof. K. (eds.)

Record type: Conference or Workshop Item (Other)

Abstract

Editorial Special Issue Power consumption is arguably becoming the most important parameter in electronic portable system design where excess power dissipation can lead to expensive and less reliable systems. Furthermore, advances in silicon technology are enabling entire systems to be fabricated on a single chip, i.e. systems-on-a-chip (SoC). The development of low power devices, circuits, algorithms and architectures, as well as CAD tools, are fundamental for the successful realisation of SoC for wireless communications and portable computing applications. This special issue is devoted to some of the recent advances in low power SoC design and test. The first three papers address SoC power minimisation at the device, circuit and architecture levels. The first paper, by R. Zhang, K. Roy, C. Koh and D. Janes, investigates device structures and interconnect architectures for multi-device-layer integrated SOI circuits. Detailed comparison with single- and double-gate SOI circuits show that multi-device-layer circuits are a viable solution for future low power high performance applications. The second paper, by R. Chang, P. Hung and I Wang, presents a new adiabatic logic called complementary pass-transistor energy recovery logic (CPERL) for low power applications. Power consumption analysis and simulation of inverters and adders based on CPERL show that CPERL circuits consume less power than those designed with NMOS energy recovery logic. The third paper, by S. Osborne, A. Erdogan, T. Arslan and D. Robinson, describes a low power bus encoding architecture targeting industrial SoC platforms. Implementation, power analysis and synthesis of the architecture are discussed and show that by using the proposed architecture a power saving of up to 22% is possible. The next three papers deal with various aspects of low power embedded systems, including energy reduction, modelling and simulation. The fourth paper, by L. Benini, A. Macii and A. Nannarelli, considers a new approach for reducing static code size and instruction fetch energy for cache-based processors. A hardware unit capable of performing on-the-fly decompression is given including its synthesis and energy estimation. The efficiency of the approach is validated using extensive benchmarking. The fifth paper, by M. Dasygenis, N. Kroupis, K. Tatas, A. Argyriou, D. Soudris and A. Thanailakis, presents a framework for designing energy and performance efficient embedded systems with emphasis on data and instruction memories. A number of multimedia examples are given illustrating the capabilities of the framework for optimising the trade-offs between performance and energy consumption. The sixth paper, by R. Muresan and C. Gebotys, describes a new macro-modelling approach for analyzing low-level current dynamics at the instruction and program level for a complex very long instruction word DSP processor core. The approach is validated with real power measurements of a DSP processor core in a VLSI chip. Developing test strategies for SoC is a challenge for a number of reasons including limited access to cores and large volumes of test data. The final paper, by P. Rosinger, P. Gonciari, B. Al-Hashimi and N. Nicolici, studies two important issues in SoC testing: scan power dissipation and volume of test data, discussing the relationship between the two. They show that the embedded core designer has the option of tuning the scan DFT hardware towards given power and test data volume constraints. The guest editors would like to thank Prof. E. Dagless for supporting the development of this special issue and to April Sparks, Linda Meller, Shirley Rossall and Stuart Govan at the IEE for their assistance in producing this issue. We would also like to sincerely thank all the authors for submitting their papers and the reviewers for keeping up with the very tight schedule that allowed us to complete this special issue as planned in less than a year. It is our sincere hope that this special issue will help augment and enhance the growing research and development efforts in low power SoC. Dr. Bashir Al-HashimiProf. Enrico MaciiProf. Kaushick Roy

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More information

Published date: September 2002
Additional Information: Special issue Address: IEE Proceedings: Computers and Digital Techniques
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 256638
URI: http://eprints.soton.ac.uk/id/eprint/256638
PURE UUID: 8e764b1c-1bb5-4c54-a8e8-fe5c3b3a5d8a

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Date deposited: 24 Jun 2002
Last modified: 18 Jul 2017 09:44

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Contributors

Editor: Prof. E. Macii
Editor: Prof. K. Roy

University divisions

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