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Behavioural Fault Modelling using VHDL-AMS and Slow Transient Analysis with hAMSter Simulator to Speed-up Analogue Fault Simulation

Behavioural Fault Modelling using VHDL-AMS and Slow Transient Analysis with hAMSter Simulator to Speed-up Analogue Fault Simulation
Behavioural Fault Modelling using VHDL-AMS and Slow Transient Analysis with hAMSter Simulator to Speed-up Analogue Fault Simulation
Two of techniques to speed-up analogue fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioural/macro modelling, whereby parts of the circuit are modelled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioural modelling as a way to speed-up fault simulation for analogue circuits. In this paper, a new behavioural fault model is developed in VHDL-AMS for a CMOS operational amplifier circuit using slow transient analysis. Simulation results confirm up to 373 times speed-up in terms of CPU time.
Kilic, Yavuz
a69ba7cd-0ab3-4f59-a863-5945028fa851
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Kilic, Yavuz
a69ba7cd-0ab3-4f59-a863-5945028fa851
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Kilic, Yavuz and Zwolinski, Mark (2002) Behavioural Fault Modelling using VHDL-AMS and Slow Transient Analysis with hAMSter Simulator to Speed-up Analogue Fault Simulation At European Test Workshop.

Record type: Conference or Workshop Item (Other)

Abstract

Two of techniques to speed-up analogue fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioural/macro modelling, whereby parts of the circuit are modelled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioural modelling as a way to speed-up fault simulation for analogue circuits. In this paper, a new behavioural fault model is developed in VHDL-AMS for a CMOS operational amplifier circuit using slow transient analysis. Simulation results confirm up to 373 times speed-up in terms of CPU time.

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More information

Published date: May 2002
Additional Information: Organisation: IEEE
Venue - Dates: European Test Workshop, 2002-05-01
Organisations: EEE

Identifiers

Local EPrints ID: 256640
URI: http://eprints.soton.ac.uk/id/eprint/256640
PURE UUID: 641c599e-5cdd-4314-adfd-0872beb24bb3
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 28 Jun 2002
Last modified: 18 Jul 2017 09:44

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Contributors

Author: Yavuz Kilic
Author: Mark Zwolinski ORCID iD

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