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Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-seeding

Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-seeding
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-seeding
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and improving the yield. Our research addresses this problem by proposing a new method which maintains the benefits of mixed-mode built-in self-test (BIST) (low test application time and high fault coverage), and reduces the excessive power dissipation associated with scan-based test. This is achieved by employing dual linear feedback shift register (LFSR) re-seeding and generating mask patterns to reduce the switching activity. Theoretical analysis and experimental results show that the proposed method consistently reduces the switching activity by 25% when compared to the traditional approaches, at the expense of a limited increase in storage requirements.
Rosinger, Paul
b4dae52c-aeb6-4e07-8a63-d6deaae76ef2
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871
Rosinger, Paul
b4dae52c-aeb6-4e07-8a63-d6deaae76ef2
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871

Rosinger, Paul, Al-Hashimi, Bashir and Nicolici, Nicola (2002) Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-seeding At International Conference on computer Design.

Record type: Conference or Workshop Item (Other)

Abstract

Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and improving the yield. Our research addresses this problem by proposing a new method which maintains the benefits of mixed-mode built-in self-test (BIST) (low test application time and high fault coverage), and reduces the excessive power dissipation associated with scan-based test. This is achieved by employing dual linear feedback shift register (LFSR) re-seeding and generating mask patterns to reduce the switching activity. Theoretical analysis and experimental results show that the proposed method consistently reduces the switching activity by 25% when compared to the traditional approaches, at the expense of a limited increase in storage requirements.

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More information

Published date: 2002
Additional Information: accepted for publication. Event Dates: September 2002
Venue - Dates: International Conference on computer Design, 2002-09-01
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 256730
URI: http://eprints.soton.ac.uk/id/eprint/256730
PURE UUID: 0a992b3d-fa5d-40d5-8a39-d23f4451e8c4

Catalogue record

Date deposited: 04 Sep 2002
Last modified: 18 Jul 2017 09:44

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Contributors

Author: Paul Rosinger
Author: Nicola Nicolici

University divisions

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