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Power Profile Manipulation: A New Approach for Reducing Test Application Time Under Power Constraints

Rosinger, Paul, Al-Hashimi, Bashir and Nicolici, Nicola (2002) Power Profile Manipulation: A New Approach for Reducing Test Application Time Under Power Constraints IEEE Transactions on Computer Aided Design of Integrated Circuits

Record type: Article

Abstract

This paper proposes a power profile manipulation approach which merges two distinct research directions in low power testing: minimization of test power dissipation and test application time reduction under power constraints. It is shown how complementary techniques can be easily combined through this approach to significantly increase test concurrency under power constraints. This is achieved in two steps: in the first step power dissipation is considered a design objective and consequently it is minimized, result further exploited in the second step, when power becomes a design constraint under which the test application time is reduced. A distinctive feature of the proposed power profile manipulation approach is that it can be included in, and consequently improve, any existing power constrained test scheduling algorithm. Extensive experimental results using benchmark circuits, considering test-per-clock as well as test-per-scan schemes, show that by integrating the proposed power profile manipulation approach into any existing power constrained test scheduling algorithm, savings up to 41 % in test application time are achieved.

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More information

Published date: October 2002
Additional Information: accepted for publication
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 256732
URI: http://eprints.soton.ac.uk/id/eprint/256732
PURE UUID: d4fb307d-d350-48fe-9a38-9f130395b674

Catalogue record

Date deposited: 08 Mar 2004
Last modified: 18 Jul 2017 09:44

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Contributors

Author: Paul Rosinger
Author: Nicola Nicolici

University divisions

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