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Scan Architecture for Shift and Capture Cycle Power Reduction

Scan Architecture for Shift and Capture Cycle Power Reduction
Scan Architecture for Shift and Capture Cycle Power Reduction
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and improv-ing the yield. Scan architectures represent the most used approach for testing digital integrated circuits. While several methods have been proposed for reducing the power dissipation due to scan shifting, very little work has been done towards reducing the power dissipation during the capture cycles. This paper proposes a method of transforming a typical scan architecture for reducing the power dissipation during both the shifting cycle and the capture cycle. The basic idea is to split the the scan chain into multiple length-balanced partitions and to enable only one partition at each test clock. This way, instead of having all the scan cells active at the same time, only a fraction of them will be active in each test clock cycle, which will reduce substantially the power dissipation in the circuit under test. Unlike previously proposed methods for shifting power reduction based on scan chain partitioning which use a single capture clock per test cycle, our approach uses multiple capture clocks per test cycle, which allows enabling only a fraction of the scan chain during each shift or capture clock, thus reducing the switching activity in the circuit under test not only during shifting but also during capture. Therefore, the proposed method represents an uni-fied solution for reducing both shifting and capture power dissipation during scan-based test. The proposed method also allows full reuse of the test vectors of the original scan architecture.
Rosinger, Paul
b4dae52c-aeb6-4e07-8a63-d6deaae76ef2
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871
Rosinger, Paul
b4dae52c-aeb6-4e07-8a63-d6deaae76ef2
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, Nicola
61efa5a6-7da8-4c33-8e68-2679a9bb0871

(2002) Scan Architecture for Shift and Capture Cycle Power Reduction Rosinger, Paul, Al-Hashimi, Bashir and Nicolici, Nicola (eds.) At International Symposium on Defect and Fault Tolerance in VLSI Systems, Canada.

Record type: Conference or Workshop Item (Other)

Abstract

Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and improv-ing the yield. Scan architectures represent the most used approach for testing digital integrated circuits. While several methods have been proposed for reducing the power dissipation due to scan shifting, very little work has been done towards reducing the power dissipation during the capture cycles. This paper proposes a method of transforming a typical scan architecture for reducing the power dissipation during both the shifting cycle and the capture cycle. The basic idea is to split the the scan chain into multiple length-balanced partitions and to enable only one partition at each test clock. This way, instead of having all the scan cells active at the same time, only a fraction of them will be active in each test clock cycle, which will reduce substantially the power dissipation in the circuit under test. Unlike previously proposed methods for shifting power reduction based on scan chain partitioning which use a single capture clock per test cycle, our approach uses multiple capture clocks per test cycle, which allows enabling only a fraction of the scan chain during each shift or capture clock, thus reducing the switching activity in the circuit under test not only during shifting but also during capture. Therefore, the proposed method represents an uni-fied solution for reducing both shifting and capture power dissipation during scan-based test. The proposed method also allows full reuse of the test vectors of the original scan architecture.

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More information

Published date: 2002
Additional Information: Event Dates: November 2002
Venue - Dates: International Symposium on Defect and Fault Tolerance in VLSI Systems, Canada, 2002-11-01
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 256750
URI: http://eprints.soton.ac.uk/id/eprint/256750
PURE UUID: 84002ce5-69ff-4bf6-ad6e-b503527ccc27

Catalogue record

Date deposited: 13 Sep 2002
Last modified: 18 Jul 2017 09:44

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Contributors

Editor: Paul Rosinger
Editor: Nicola Nicolici

University divisions

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