Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems
This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.
90-95
Wu, D.
325ef387-856f-49f6-bc2d-2ef44d7e6f82
Al-Hashimi, B. M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Eles, P.
2785f3c8-8df5-499f-9698-b3518e7dcda0
2003
Wu, D.
325ef387-856f-49f6-bc2d-2ef44d7e6f82
Al-Hashimi, B. M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Eles, P.
2785f3c8-8df5-499f-9698-b3518e7dcda0
Wu, D., Al-Hashimi, B. M. and Eles, P.
(2003)
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems.
Design, Automation and Test in Europe, Munich, Germany.
03 - 07 Mar 2003.
.
Record type:
Conference or Workshop Item
(Other)
Abstract
This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.
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Published date: 2003
Additional Information:
Event Dates: 3-7 March 2003
Venue - Dates:
Design, Automation and Test in Europe, Munich, Germany, 2003-03-03 - 2003-03-07
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 257386
URI: http://eprints.soton.ac.uk/id/eprint/257386
PURE UUID: 7f2b0482-2882-4959-ab0c-7d0c423868e2
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Date deposited: 06 May 2003
Last modified: 10 Dec 2021 20:50
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Contributors
Author:
D. Wu
Author:
B. M. Al-Hashimi
Author:
P. Eles
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