Wu, D., Al-Hashimi, B. M. and Eles, P.
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems
At Design, Automation and Test in Europe, Germany.
03 - 07 Mar 2003.
Full text not available from this repository.
This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.
Conference or Workshop Item
||Event Dates: 3-7 March 2003
|Venue - Dates:
||Design, Automation and Test in Europe, Germany, 2003-03-03 - 2003-03-07
||Electronic & Software Systems
||06 May 2003
||17 Apr 2017 22:52
|Further Information:||Google Scholar|
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