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Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems

Record type: Conference or Workshop Item (Other)

This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.

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Citation

Wu, D., Al-Hashimi, B. M. and Eles, P. (2003) Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems At Design, Automation and Test in Europe, Germany. 03 - 07 Mar 2003. , pp. 90-95.

More information

Published date: 2003
Additional Information: Event Dates: 3-7 March 2003
Venue - Dates: Design, Automation and Test in Europe, Germany, 2003-03-03 - 2003-03-07
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 257386
URI: http://eprints.soton.ac.uk/id/eprint/257386
PURE UUID: 7f2b0482-2882-4959-ab0c-7d0c423868e2

Catalogue record

Date deposited: 06 May 2003
Last modified: 18 Jul 2017 09:39

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Contributors

Author: D. Wu
Author: P. Eles

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