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Investigating 50nm channel length vertical MOSFETs containing a dielectric pocket in a circuit environment

Investigating 50nm channel length vertical MOSFETs containing a dielectric pocket in a circuit environment
Investigating 50nm channel length vertical MOSFETs containing a dielectric pocket in a circuit environment
499-502
Donaghy, D.C.
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Hall, S.
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Kunz, VD
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de Groot, C.H.
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Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Donaghy, D.C.
4a2f50ed-d9a3-49d2-a405-bc3638486769
Hall, S.
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
Kunz, VD
c21549be-6367-48d6-bec7-ea23112654a9
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Donaghy, D.C., Hall, S., Kunz, VD, de Groot, C.H. and Ashburn, P. (2002) Investigating 50nm channel length vertical MOSFETs containing a dielectric pocket in a circuit environment. ESSDERC 2002. pp. 499-502 .

Record type: Conference or Workshop Item (Other)
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More information

Published date: 2002
Venue - Dates: ESSDERC 2002, 2002-01-01
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 257759
URI: http://eprints.soton.ac.uk/id/eprint/257759
PURE UUID: 675b1ecb-7deb-452e-b0ed-95033f6cae7f
ORCID for C.H. de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 26 Jun 2003
Last modified: 10 Dec 2019 01:48

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Contributors

Author: D.C. Donaghy
Author: S. Hall
Author: VD Kunz
Author: C.H. de Groot ORCID iD
Author: P. Ashburn

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