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Symbolic Model Checking of Dual Transition Petri Nets

Symbolic Model Checking of Dual Transition Petri Nets
Symbolic Model Checking of Dual Transition Petri Nets
This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models [12], using model checking techniques. The methodology presented addresses the symbolic model checking of embedded systems behavioural properties, expressed in either computation tree logics (CTL) or linear temporal logics (LTL). The embedded system specification is given in terms of DTPN models, where elements of the model are captured in a four-module library which implements the behaviour of the model. Key issues in the development of the methodology are the heterogeneity and the nondeterministic nature of the model. This is handled by introducing some modifications in both structure and behaviour of the model, thus reducing the points of nondeterminism. Several features of the methodology are discussed and two examples are given in order to show the validity of the model.
43-48
Varea, Mauricio
7a752b8b-0f8b-47e0-b411-2ac53f228ba7
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Cortes, Luis A.
01eb46c4-11cb-4c96-97db-bee34e117ab0
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
Peng, Zebo
c0500005-3976-42df-974f-581eb1d39589
Varea, Mauricio
7a752b8b-0f8b-47e0-b411-2ac53f228ba7
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Cortes, Luis A.
01eb46c4-11cb-4c96-97db-bee34e117ab0
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
Peng, Zebo
c0500005-3976-42df-974f-581eb1d39589

Varea, Mauricio, Al-Hashimi, Bashir M., Cortes, Luis A., Eles, Petru and Peng, Zebo (2002) Symbolic Model Checking of Dual Transition Petri Nets At International Symposium on Hardware/Software Codesign (CODES), United States. 06 - 08 May 2002. , pp. 43-48.

Record type: Conference or Workshop Item (Paper)

Abstract

This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models [12], using model checking techniques. The methodology presented addresses the symbolic model checking of embedded systems behavioural properties, expressed in either computation tree logics (CTL) or linear temporal logics (LTL). The embedded system specification is given in terms of DTPN models, where elements of the model are captured in a four-module library which implements the behaviour of the model. Key issues in the development of the methodology are the heterogeneity and the nondeterministic nature of the model. This is handled by introducing some modifications in both structure and behaviour of the model, thus reducing the points of nondeterminism. Several features of the methodology are discussed and two examples are given in order to show the validity of the model.

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More information

Published date: May 2002
Additional Information: Event Dates: 6-8 May 2002 Organisation: IEEE/ACM Address: Colorado, USA
Venue - Dates: International Symposium on Hardware/Software Codesign (CODES), United States, 2002-05-06 - 2002-05-08
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 257837
URI: http://eprints.soton.ac.uk/id/eprint/257837
PURE UUID: afb49618-daad-4584-9c8c-85e39583ddad

Catalogue record

Date deposited: 25 Jun 2003
Last modified: 18 Jul 2017 09:35

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Contributors

Author: Mauricio Varea
Author: Luis A. Cortes
Author: Petru Eles
Author: Zebo Peng

University divisions

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